Fig. 1. FEA models of flip chip bond and die attach were illustrated as (a, b) and (c, d), respectively. Each type has two kinds of molding processes, one is the molding epoxy covered onto the silicon substrate as (b, d), another is the molding epoxy has a gap with MEMS chip as (a, c).
Fig. 3. The heating history for epoxy molding process
Fig. 4. The schematic pictures for two boundary conditions at the bottom surface of copper substrate (a) Boundary
condition type 1 is fixed end; and (b) Boundary condition type 2 is sliding end.
Results and Discussion
Fig. 5. The thermal stresses in membrane during heating history for flip chip bonding and wire bonding are shown in the (a) and (b), respectively. The BC1and BC2 are indicated the fixed-end and sliding boundary on the surface of substrate, respectively
Table I. The coefficients of materials for simulation
Fig. 6. The distribution of thermal stress for (a) flip chip bond and (b) die attach with sliding-end boundary as the temperature
?at 200℃. The maximum stress occurred at the interface between modeling epoxy and copper substrate for flip chip bond,
?but the maximum stress occurred at the interface between modeling epoxy and silicon substrate for die attach.
The mismatch of CTE for the heterostructure during the packaging processing of MEMS device can induce the residual stress within the diaphragm to yield the variation of performance, consequently, the molding material with a lower CTE and elastic modulus can effectively reduce the thermal stress. And, flip chip bond is a more proper way for packing of MEMS device with membrane structure.
This project was founded by Micro System Technology Center at Industrial Technology Research Institute (ITRI) Southern. In addition, we are grateful to the National Center for High-Performance Computing for the computer time and facilities